Home > Solutions > HD FIFO
 


Other Solutions:

H.264 Video Streaming

Video Conversion

LCD Display

Multiple Video Display

Video Decoding

FIFO Memory
 
HD-FIFO Modules + HSMC Adaptor Board
EOL
 

AL460A-7-EVB-A0 & AL460-13-EVB-A0 - 4.8 Gbps HD-FIFO modules with HSMC interface for Altera's Cyclone III FPGA Starter Kit (EOL)

 

 


Introduction

This EVB board is designed for evaluating the AL460A HD-FIFO integrated chip. It has two embedded AL460A-7-PBF (or AL460A-13-PBF) chips operating in parallel, expanding the bus width to 32-bits. Control signals and data bus signals are available on two 50-pin connectors; one connector is reserved for write controls and the input data bus; the other one is for read controls and the output data bus. A separate adaptor board (HSMC interface) is available to the user for connecting the module directly to an Altera's Cyclone III FPGA Starter Kit for any necessary solution verification/ validation.

The AL460 chip is designed with a straightforward bus interface, reducing implementation and debugging efforts, and helping customers develop faster and more efficiently. This board is especially designed and optimized to be easily integrated as an add-on module on existing systems, significantly reducing interface engineering issues commonly found in retrofit efforts. This allows designers the luxury of being able to focus on core functionality and product quality.

  

 


General Features

  • 256 Mbit density, 8M x 32-bit FIFO memory
  • Maximum 150 MHz, 32-bit synchronous sequential read/write operations
  • Maximum 4.8 Gbps throughput
  • 3.3V power supply
  • Programmable I/O control
  • Supports double buffer mode (4M x32-bit upper and lower frames access)
  • Selectable Polarity control

 
Advantages

HD-FIFO is a proprietary design technology used to overcome issues commonly hindering and limiting other frame buffer devices (e.g. SDRAM, DDR…etc) found in FPGA solutions. Traditional FPGA implementations require higher I/O pin totals and place heavy demands on logic resources and property memory controllers, forcing a designer to move up to higher grade FPGAs. In contrast, AverLogic’s HD-FIFO requires significantly less in I/O pins and logic resources, at the same time overcoming latency issues therein. The programmable I/O controls and double buffer mode increase design flexibility and reduce FPGA overhead.

 

AL460A HD FIFO and Bitec's DVI Daughter Cards with HSMC interface for Altera's 3C120 Development kit





Click HERE for more info. on Bitec's HSMC DVI daughter card

 

 






Click HERE for more info. on Altera's Cyclone III FPGA Starter Kit

Click HERE for more info. on HSMC interface

Click HERE for more info. on all Altera's Daughter Cards
 




Functional Block Diagram



     

 

AL460A EVB Flyer

AL460A-7&13-EVB-A0 User Manual

AL460A chipset information